1. Field of the Invention
The present invention relates to a shared register control system in a multiprocessor computer system.
2. Prior Art
Conventionally, as this kind of shared register control system, the following system has been proposed, in which, first, the same number of shared registers as that of processors is previously made to correspond one to one to the processor and, normally, each processor uses a specific shared register. Sharing of the register between the processors is achieved by logically dividing a plurality of processors into a master and slave processors so that a shared register used by the master processor, which corresponds to the same processor, may be shared with the slave processors, or its sharing is canceled (master/slave system).
According to the above-described prior art shared register control system, a shared register corresponding to a specific processor, which has been used for a task operating on the master processor, is shared among other tasks operating on the slave processors so that the tasks may communicate among each other via the same shared register.
In addition, if the task is switched on the slave processor and another task runs, which no longer uses the shared register corresponding to the master processor, then a shared register corresponding to that slave processor may be allocated to that another task to allow it to be executed. On the other hand, since the register corresponding to the master processor is not shared with the slave processors any more, another task can be executed by using it. However, since the master processor cannot exclusively share the registers corresponding to the other processors, as long as, for example, the slave processor continues to use the shared register corresponding to the master processor, the task being executed on the master processor cannot be switched to any other task to use the shared register thereon.